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Barefoot’s Tofino 2 chip delivers 12.8 Tbps switching for 32x400GE

Barefoot Networks is now sampling its Tofino 2 chip, the second generation of its P4-programmable Tofino Ethernet switch application-specific integrated circuit (ASIC) family.

Tofino 2 doubles the performance of the first generation Tofino chip, now delivering 12.8 Tbps of packet processing capacity for hyperscale data centers, cloud, enterprise and service provider networks. The device leverages 7nm process technology and is designed for full P4-programmability.

Tofino 2 highlights:

“Until Tofino arrived in 2016, networking switch ASICs hadn’t changed much in 20 years; they all ran pretty much the same tired old features. Our industry is stuck in a dinosaur way of doing things, and it takes years to add new features,” said Nick McKeown, Co-Founder, and Chief Scientist at Barefoot Networks. “Thankfully, networking is changing. Tofino, the first chip based on the PISA architecture, moved protocols – old and new – up and out of hardware into software, where they evolve at the pace of software. Tofino started it, now Tofino 2, at twice the capacity and twice the resources, demonstrates there is no going back. Within five years all switches will be programmable. We believe programming your network should be as easy as programming your computer.”

Customers cited in the Barefoot press release include Goldman Sachs, Cisco, Alibaba Infrastructure Services, Tencent, Baidu, JD Cloud, and Ucloud.

https://www.barefootnetworks.com/products/brief-tofino-2/

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