Converge Digest

Innovium enhances its Ethernet Switching Architecture

Innovium outlined a series of enhancements for its TERALYNX architecture for enabling top-to-bottom, 1T to 51.2T+ performance scalability along with programmability, telemetry, low latency and large on-chip buffers.

Innovium’s Enhanced TERALYNX architecture consists of:

Innovium said these breakthrough innovations span a variety of areas including data-structures, algorithms, ground-up architecture and R&D flow and deliver up to 2x capabilities and performance in the same silicon area vs alternatives. This technology has been silicon proven as part of the production-ready TERALYNX 7, which delivered the best feature-set 12.8T switch silicon, with lowest-latency in 16nm and smallest silicon area. The enhanced architecture further optimizes silicon area and data-center features to expand the performance range and address Edge, Enterprise and 5G data-centers. This allows Innovium to deliver capabilities one process node earlier than alternatives along with unique top-to-bottom scalability, which translates to faster time to market and lower R&D investment for customers.

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