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Innovium pushes switching silicon to 25.6 Tbps with support for 112G PAM4

Innovium unveiled its TERALYNX 8 networking switch silicon featuring a massive 25.6 Tbps capacity and support for 112G PAM4 SerDes I/O. This next-generation TERALYNX 8 design features deep programmability, the largest on-chip buffers, and advanced telemetry capabilities.

Innovium’s TERALYNX 8 switch, which is aimed at hyperscale data centers and which is expected to sample in the second half of 2020, could be used for highly compact, highest port-density single-chip switches for 100G to 800G configurations, including 1RU, 32 x 800G switch. The silicon will be delivered in a single 7nm die fabricated by TSMC.

Innovium confirmed that its current generation, 12.7 Tbps switching silicon is already being used by numerous commercial customers, including some of the biggest cloud provider networks.

Some TERALYNX 8 highlights

“We are excited to see several top cloud customers deploying our industry-leading TERALYNX 7 based switches. They are experiencing tremendous growth from workloads such as AI, HPC and dis-aggregated storage and looking for significantly higher networking performance,” said Rajiv Khemani, CEO and Co-Founder of Innovium Inc. “Leveraging our modern, ultra-efficient TERALYNX architecture, we are pleased to launch TERALYNX 8 that addresses critical requirements of performance, latency, analytics and quality for next generation data-center networks.”

Innovium is headquartered in San Jose, California, with design centers in Portland, Oregon, and Bengaluru, India.

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