A new integrated circuit design called a Logic Processing Array (LPA) promises to deliver scalable and parallel processing across a sea of processing elements in real-time.
The innovative architecture enables Boolean logic processes to run on all processing elements concurrently without a clock.
The processing speed delivered by the Logic Processing Array offers an order of magnitude advantage over conventional circuit designs, according to a white paper written by Peter-Paul Troendle on behalf of 3wa Technologies, Robert Erra from the Computing Department at Ecole Supérieure d’Electronique Informatique & Automatique in Paris, and Nicolas Alachiotis from Computing Research at Carnegie Mellon University and an Assistant Professor at the University of Twente.
The white paper presents the results of tests conducted using a universally accepted test paradigm known as “Levenshtein/Edit Distance,” which is a computational test that allows testers to compare their results to others using available technology.
The key takeaways from the paper are:
- The Logic Processing Array is clock-less, lag-less, and asynchronous, offering true concurrent parallel processing without the need for memory.
- It is a network of tightly coupled nodes or processing elements that can be hardwired or software-configured for specific applications.
- The logic array operates as an unclocked architecture, with computation propagating through the entire fabric until resolved, and sequential operations controlled by routing through the NULL state.
- The Logic Processing Array provides a unique blend of parallelism, data flow, and regularity, making it a powerful alternative to traditional architectures for high-performance computing.
- It simplifies design, eliminates timing issues, and achieves O(1) complexity for certain use cases.
In summary, logic arrays offer a unique blend of parallelism, data flow, and regularity, making them a powerful alternative to traditional architectures. Their rhythmic, asynchronous nature opens up exciting possibilities for exponential increases in computing power for high-performance computing.
The full paper is below.