As AI workloads push data center infrastructure to the limit, the industry’s need for faster, more efficient interconnects has never been more acute. That urgency was front and center at a sold-out workshop hosted by the OIF in Santa Clara, California, where discussion focused on the path to 448G per lane — the next major leap in networking, paving the way to 3.2T interfaces between XPUs.
Moderated by OIF President Nathan Tracy (TE Connectivity), the panel featured senior representatives from IEEE, SNIA, the Ethernet Alliance, the Ultra Ethernet Consortium, and the new Ultra Accelerator Link Consortium. Their message was unified: the jump from 224G to 448G will be the most challenging so far—and also the most essential, driven by hyperscale AI clusters that demand ultra-low latency, massive bandwidth, and energy efficiency at scale.
In terms of technology evolution, 448G raises the bar, with little room for margin and immense pressure on power and thermal budgets. For AI data center operators training trillion-parameter models, interconnect bandwidth has become as important as compute itself.
Panelist Highlights
Kurtis Bowman – Chair, Ultra Accelerator Link Consortium; Director, Architecture and Strategy, AMD
- Bowman leads the UALink Consortium, an open standard initiative to interconnect thousands of AI accelerators with shared memory models.
- UALink recently launched its 1.0 specification in under a year—a rapid development cycle reflecting hyperscaler urgency.
- The standard supports up to 1.6 Tbps of bidirectional bandwidth and connects as many as 1,000 accelerators.
- He emphasized that latency, power, and die size are critical metrics, and that UALink aims to make distributed accelerators behave like a single GPU.
- Bowman cautioned that the industry cannot afford slow-moving standards processes—“We need to move at AI speed.”
Anthony Constantine – Distinguished Member of Technical Staff, Micron; SNIA Technical Council Representative
- Constantine represents SNIA’s SFF Technical Affiliate (SFF TA), which focuses on physical-layer interconnects like SFP/QSFP and is vital to next-gen Ethernet modules.
- SNIA has published over 150 specs, with 13 new or revised in the last year and over 70 active member companies.
- He announced that SNIA recently kicked off work on the 448G SFF-TA-1043 project for compute and storage backplanes.
- Emphasized SNIA’s protocol-agnostic stance, working with OIF, IEEE, and other groups to accelerate spec development.
- “We need to knock out the low-hanging fruit fast,” he said, urging tight cooperation to keep timelines aligned.
John D’Ambrosia – Distinguished Engineer, Futurewei; Chair, IEEE 802.3 NEA “Ethernet for AI” Assessment
- D’Ambrosia noted that the collaboration between standards groups started earlier than ever—something he hasn’t seen in 20 years of leading Ethernet projects.
- IEEE 802.3 has now formalized liaison relationships with OIF, SNIA, and others to ensure tight coordination.
- He argued that not all networks in AI data centers are the same—front-end, scale-up, and scale-out each have different latency and bandwidth requirements.
- New speeds like 3.2 Tbps and 6.4 Tbps may require expanding from 8 to 16 lanes; trade-offs between reach, resilience, and latency must be openly debated.
- “Let’s stop assuming that low latency is always king,” he said. “The priorities are shifting.”
Mark Nowell – Cisco Fellow, Cisco; Technical Contributor, Ultra Ethernet Consortium (UEC)
- Nowell outlined UEC’s vision: a high-performance, Ethernet-based fabric optimized for AI/ML at hyperscale.
- The consortium operates under the Linux Foundation and now includes 120+ companies and 1,500+ active contributors.
- Its v1.0 spec (coming soon) targets scale-out AI clusters with optimized transport protocols, including link-layer retry and credit-based flow control.
- Nowell warned of “amplification effects” from scale—where small inefficiencies in power, reliability, or topology multiply across tens of thousands of nodes.
- Liquid cooling and physical layer reliability are now essential design considerations as system sizes grow.
David Rodgers – Chair, Events & Conferences Committee, Ethernet Alliance; Senior Product Line Manager, EXFO
- Rodgers positioned the Ethernet Alliance as a “neutral Switzerland” enabling multi-vendor interoperability across protocols and standards bodies.
- The Alliance hosts Plugfests and public showcases (e.g., at OFC) to validate interoperability for new specs like 224G and upcoming 448G.
- He emphasized the role of certification, citing past success with Power over Ethernet (PoE) programs to reduce confusion and accelerate deployment.
- The Alliance also curates the widely used Ethernet Roadmap, helping vendors and customers align expectations.
- “At the end of the day, it has to just work. That’s our job,” Rodgers said.
Nathan Tracy – President, OIF; Technologist, System Architecture Team, TE Connectivity
- Tracy closed the panel by highlighting how OIF historically delivered electrical interface specs from 28G to 224G—but said 448G is a whole new level of difficulty.
- The OIF’s new 448G Framework Project is addressing challenges across signal integrity, modulation, DSP, thermal, and alignment between electrical and optical interfaces.
- He warned that consensus is harder and timelines are tighter than ever before, due to surging AI infrastructure demands.
- Tracy also introduced OIF’s Energy Efficient Interfaces (EEEI) initiative, focused on scaling power-aware solutions across fabric types.
- “Our job is to find the point where everyone is equally uncomfortable,” he said, describing the consensus process behind every successful standard.
