Samsung introduced two new advanced semiconductor nodes, SF2Z and SF4U, and unveiled its integrated Samsung AI Solutions platform, leveraging the strengths of its Foundry, Memory, and Advanced Package (AVP) businesses. At its annual Samsung Foundry event in San Jose, California, Samsung executives emphasized the company’s unique ability to company the latest process node, advanced packaging, and high-bandwidth memory (HBM) for customers targeting the latest AI silicon designs.
- The SF2Z, Samsung’s latest 2nm process, features an optimized backside power delivery network (BSPDN) technology. This innovation places power rails on the wafer’s backside to reduce bottlenecks between power and signal lines, enhancing power, performance, and area (PPA) compared to the first-generation SF2 node. The SF2Z process is scheduled for mass production in 2027. Meanwhile, the SF4U is a high-value 4nm variant offering PPA improvements through optical shrinkage, with mass production set for 2025.
- Samsung also confirmed that its preparations for the SF1.4 (1.4nm) process are on track, aiming for mass production in 2027. The company is focusing on material and structural innovations to develop future technologies below 1.4nm.
Additionally, Samsung plans to launch an all-in-one, co-packaged optics (CPO) integrated AI solution in 2027, designed to offer high-performance, low-power semiconductors optimized for AI applications. This initiative is part of Samsung’s broader strategy to provide comprehensive AI solutions.
“At a time when numerous technologies are evolving around AI, the key to its implementation lies in high-performance, low-power semiconductors,” said Dr. Siyoung Choi, President and Head of Foundry Business at Samsung Electronics. ”Alongside our proven GAA process optimized for AI chips, we plan to introduce integrated, co-packaged optics (CPO) technology for high-speed, low-power data processing, providing our customers with the one-stop AI solutions they need to thrive in this transformative era.”
The Samsung Foundry event also featured presentations from Arm CEO Rene Haas and Groq CEO Jonathan Ross.
Around 30 partner companies exhibited at booths, further highlighting the dynamic collaboration across the Samsung Foundry ecosystem.
- Cadence Design Systems has announced a collaboration with Samsung Foundry to advance technology for AI and 3D-IC semiconductor design on Samsung’s gate-all-around (GAA) nodes. This partnership aims to enhance development for applications such as AI, automotive, aerospace, hyperscale computing, and mobile. Key achievements include the use of Cadence.AI to reduce leakage power by over 10% on the SF2 GAA platform and the certification of a complete Cadence backside implementation flow for Samsung’s SF2 node. This collaboration has led to successful development and validation of a test chip, demonstrating readiness for advanced design implementations.
- Synopsys announced that its AI-driven digital and analog design flows have been certified on Samsung Foundry’s SF2 process, with multiple test chip tapeouts. Utilizing the Synopsys.ai™ full-stack EDA suite, these reference flows improve performance, power, and area (PPA), enhance productivity, and speed up analog design migration for Samsung’s Gate-All-Around (GAA) process technologies. The certification was achieved through Synopsys’ AI-driven design technology co-optimization (DTCO) solution, which provided superior PPA outcomes. These techniques will also be applied to Samsung’s upcoming SF1.4 process.
- Samsung Electronics is investing $17 billion in a new semiconductor fabrication facility in Taylor, Texas. The 1.1 million square foot fab will use advanced 3-nanometer process technology and is expected to start production in the second half of 2024. The facility will have a capacity of around 170,000 wafers per month, making it one of the largest and most advanced semiconductor manufacturing facilities in the world. The project is expected to create around 1,800 new jobs in the region.