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Synopsys and Samsung Boost AI and Multi-Die Design

Synopsys and Samsung Foundry have expanded their collaboration to advance the design of next-generation AI, HPC, and multi-die systems on Samsung’s most advanced nodes, including SF2 and SF2P. The companies’ joint efforts are helping customers accelerate tape-outs of complex SoCs and multi-die designs using Synopsys’ AI-driven EDA tools, IP portfolio, and 3DIC Compiler, optimized for Samsung’s latest process technologies.

The latest milestone includes a successful customer tape-out of an HBM3 design on Samsung’s SF2 process and I-CubeS 2.5D packaging, with Synopsys’ 3DIC Compiler reducing turnaround time by 10x and improving eye opening by 6% for enhanced performance. Synopsys’ certified digital and analog flows on SF2P, powered by the Synopsys.ai full-stack EDA suite, are helping customers achieve superior PPA results while accelerating the migration of analog IP to advanced nodes. Additionally, a broad portfolio of Synopsys IP—including 224G, UCIe, PCIe 7.0, MIPI, LPDDR6, and USB4—is now optimized for Samsung’s SF2P, SF4X, and other leading-edge processes.

The expanded collaboration is driving innovation for a wide range of applications, from AI inference engines for data centers to ultra-efficient edge AI devices and advanced HPC platforms. The combined design technology co-optimization (DTCO) and certified IP portfolio enable Samsung Foundry customers to reduce design risk and time-to-market for complex multi-die and AI-driven architectures.

“Together with Samsung Foundry, we’re enabling the most advanced AI processors across a broad spectrum of use cases, from high-performance AI inference engines to ultra-efficient Edge AI devices,” said John Koeter, senior vice president, Synopsys IP Group.

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