Synopsys and TSMC have expanded their long-standing collaboration with certified EDA flows and IP solutions for the latest angstrom-scale nodes, including TSMC’s A16 and N2P processes. The companies are enabling advanced SoC and 3DIC design with AI-driven digital and analog design flows, CoWoS packaging support, and comprehensive IP portfolios optimized for ultra-low power and high-performance compute.
Certified flows built on Synopsys.ai enhance migration, frequency optimization, and backend routing for advanced nodes. Synopsys’ IC Validator™ is now certified for both A16 and N2P, with 3Dblox-ready 3DIC verification capabilities and scalable PERC rule support for ESD analysis. Synopsys 3DIC Compiler supports TSMC’s CoWoS platform with up to 5.5x reticle interposers and multi-die integration workflows powered by integrated thermal, power, and signal integrity analysis.
Synopsys also offers a robust portfolio of silicon-proven IP for leading-edge standards, including 1.6T Ethernet, PCIe 7.0, UCIe, HBM4, and UALink. These IP blocks are optimized for deployment on TSMC’s N2/N2P processes and are designed to reduce risk and accelerate time-to-market for next-generation AI, HPC, and automotive chips.
- Certified Synopsys EDA flows now support TSMC’s A16 and N2P nodes, with work underway for A14.
- Synopsys.ai enables AI-driven optimization for analog, digital, and RF migration at advanced nodes.
- 3DIC Compiler supports TSMC CoWoS with 5.5x reticle-sized interposers and 3Dblox standard.
- Broad IP portfolio includes PHYs and controllers for PCIe 7.0, HBM4, Ethernet, UCIe, LPDDR6, and Ultra Ethernet.
- IC Validator enables A16/N2P signoff with enhanced DRC, LVS, and ESD verification performance.
“Together, we are delivering future-ready solutions that empower engineers to push the boundaries of technology,” said Sanjay Bali, SVP of Strategy and Product Management at Synopsys.