TeraSignal has announced successful interoperability testing between its TSLink intelligent chip-to-module (C2M) interconnect and Synopsys’ 112G Ethernet PHY IP. This collaboration highlights advancements in low-power, low-latency optical connectivity for AI and data center infrastructure. TSLink supports real-time diagnostics, optimized link settings, and a plug-and-play interface, simplifying integration with linear optics for large-scale ASICs.
The joint solution is designed to enhance deployment of Linear Pluggable Optics (LPO), Near Package Optics (NPO), and Co-Packaged Optics (CPO). With support for PCIe 64Gbps and Ethernet 106Gbps standards, TSLink offers broad compatibility and protocol-agnostic design. By eliminating the need for DSPs, TSLink achieves up to 50% power savings and reduced latency, addressing the demands of hyperscale AI networks and compute-intensive applications such as machine learning and data center switching.
The demonstration will be showcased at at DesignCon 2025 in Santa Clara, California from January 28–30, featuring interoperability between TeraSignal’s TSLink interconnect and Synopsys’ silicon-proven 112G Ethernet PHY IP. The event underlines a shared commitment to advancing high-speed optical interconnect technology.
• Demonstration of TSLink interoperability with Synopsys’ 112G Ethernet PHY IP.
• Optimized for AI, machine learning, and high-performance data centers.
• Supports PCIe 64Gbps and Ethernet 106Gbps standards.
• Reduces power consumption by 50% and minimizes latency by eliminating DSPs.
• Enables seamless integration for LPO, NPO, and CPO deployments.
“Interoperability between TeraSignal’s TSLink and Synopsys’ 112G Ethernet PHY IP sets a new benchmark for intelligent interconnects, reducing design risk and advancing AI and data center infrastructure,” said Dr. Armond Hairapetian, Founder and CEO of TeraSignal.
TeraSignal will also demo its TS5602 Intelligent Re-Driver, which supports 4x64Gb/s PCIe connectivity and is available in a compact 7.25mm x 5.25mm FCLGA package as well as a flip chip bumped die. Key features include:
- Over 50% power reduction compared to DSP-based retimers.
- Low latency through DSP-free architecture.
- Digital eye monitoring for real-time BER visibility on every link.
- Automatic link training powered by TSLink software for streamlined setup.
- Automatic receiver detection for PCIe use cases.
