Tilera, a start-up based in Santa Clara, California, launched its first “TILE64” processor containing 64 full-featured, programmable cores, each capable of running Linux. The on-chip architecture is designed to scale to hundreds and even thousands of cores. Tilera claims 10X the performance and 30X the performance-per-watt of the Intel dual-core Xeon, and 40X the performance of the leading Texas Instruments DSP.
Initial target markets for the TILE64 processor include the embedded networking and digital multimedia markets. This could include switches and security appliances with the performance of up to 20 Gbps for L4-L7 services. In the digital video and multimedia market, the TILE64 could deliver two streams of broadcast-quality, high-definition H.264-encode capability in a single chip, and more than ten streams of encode for high-definition video conferencing applications.
The company is pioneering an “iMesh” Interconnect architecture that eliminates the on-chip bus interconnect, which it sees as the central bottleneck through which all packets from multiple cores must flow.
Tilera eliminates the bus by placing a communications switch on each processor core and arranging them in a grid fashion on the chip.
Tilera said this creates an efficient 2-dimensional traffic system for packets. Because the aggregate bandwidth is orders of magnitude greater than a bus and the distance between cores is shorter, the iMesh technology can be leveraged to create grids as large or small as an application requires, creating a “computing-by-the-yard” scalability.
In order to minimize total system power, cost and real estate, the TILE64 processor integrates four DDR2 memory controllers and an array of high speed I/O interfaces, including two 10 Gbps XAUI, two 10 Gbps PCIe, two 1 Gbps Ethernet RGMII, and a programmable flexible I/O interface to support interfaces such as compact flash and disk drives.
http://www.tilera.com
- Tilera was founded in 2004 to bring to market the MIT research of Dr. Anant Agarwal who first created the mesh-based multicore architecture in 1996. The “Raw” project received multi-million dollar DARPA and National Science Foundation grants and spawned the development of the first tiled multicore processor prototype and associated multicore software in 2002.
- Tilera is venture funded by Bessemer Venture Partners, Walden International, Columbia Capital and VentureTech Alliance.