
Key features include:
- Dataflow architecture featuring 448 PISC processor cores and 28 engine access points to connect to on-chip or off-chip table memory and hardware engines
- Advanced traffic manager with hierarchical per-user, per-service scheduling and shaping and deep off-chip packet buffer fully implemented in DDR3 DRAM
- Embedded switching with advanced pre-classification for intelligent oversubscription
- Internet-scale forwarding of IPv4 and IPv6 through high-performance memory interfaces to off-chip TCAM, SRAM and DDR3 DRAM
Synchronous Ethernet and support for one-step PTP IEEE-1588.
“The high demand for the HX family of NPUs is due to its combination of low power consumption, programmable wirespeed processing and integration of advanced traffic management,” said Anders Ericsson, Xelerated VP Sales and Marketing. “We are thrilled about some of our new customer projects now going into production. These platforms have the potential to reshape the Carrier Ethernet market.”
http://www.xelerated.com