Marvell announced its first 2nm silicon IP, developed on TSMC’s advanced 2nm process, marking a major step in AI and cloud infrastructure innovation. The new platform is designed to enable custom AI accelerators, CPUs, networking solutions, and high-performance switches that will help hyperscalers boost performance and efficiency in AI-driven workloads. Marvell’s building block approach integrates high-speed SerDes, die-to-die interconnects, silicon photonics, high-bandwidth memory (HBM) architectures, and advanced packaging technologies, setting the foundation for next-generation data infrastructure.
One of the key innovations in Marvell’s 2nm platform is the introduction of 3D simultaneous bi-directional I/O, capable of operating at 6.4 Gbps for vertically stacked die inside chiplets. Unlike traditional unidirectional I/O, this new approach doubles bandwidth efficiency or reduces interconnect complexity by 50%, making it ideal for 2.5D, 3D, and 3.5D chip designs. As 30% of advanced node processors are expected to adopt chiplet-based architectures, this breakthrough will allow for taller die stacks that function as a single monolithic device while offering enhanced performance and scalability.
Marvell has been a leader in advanced silicon development, launching the first 5nm data infrastructure platform in 2020 and its 3nm platform in 2022, with custom silicon products now shipping. The company’s longstanding collaboration with TSMC has played a crucial role in pushing high-density, high-performance transistor designs, ensuring faster development cycles for AI-driven infrastructure. Marvell will continue refining its 2nm technology to support the growing custom silicon market, which is projected to account for 25% of accelerated compute by 2028.
• Marvell unveils its first 2nm silicon IP, developed on TSMC’s advanced process technology.
• Platform enables next-gen AI accelerators, CPUs, networking, and cloud infrastructure solutions.
• 3D simultaneous bi-directional I/O operates at 6.4 Gbps, doubling bandwidth efficiency for chiplet-based architectures.
• 30% of advanced node processors are expected to use chiplet designs, benefiting from higher stacking flexibility.
• Marvell continues its advanced silicon roadmap, following 5nm (2020) and 3nm (2022) platform launches.
• Custom silicon expected to represent 25% of the accelerated compute market by 2028.
“Our longstanding collaboration with TSMC plays a pivotal role in helping Marvell develop complex silicon solutions with industry-leading performance, transistor density, and efficiency,” said Sandeep Bharathi, Chief Development Officer at Marvell.
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