Cadence has expanded its multi-year partnership with Samsung Foundry to accelerate advanced SoC, 3D-IC, and chiplet designs for AI data centers, automotive, and next-gen connectivity. The collaboration now includes an extended IP agreement and joint development of AI-driven design flows on Samsung’s advanced SF2P, SF4X, SF5A, and SF4U process nodes.
The latest milestone certifies Cadence’s AI-driven digital full flow and physical verification tools for Samsung’s SF2P node, supporting key innovations such as Hyper Cell and LLE 2.0 technologies. Cadence also demonstrated analog IP migration from 4nm to 2nm and delivered an RF chip/package co-design flow for mmWave apps on Samsung’s 14nm FinFET. In 3D-IC design, Cadence and Samsung showcased advanced power integrity analysis, with Voltus InsightAI resolving 80-90% of IR-drop violations on SF2-based high-speed CPUs.
The new IP agreement covers LPDDR6, GDDR7, PCIe 6.0/5.0, CXL 3.2, UCIe-SP, and tailored automotive PHY IP, helping designers accelerate development of AI/HPC SoCs, automotive ADAS platforms, and RF connectivity systems with reduced risk and faster time to market.
- Expanded Cadence-Samsung IP agreement for SF4X, SF5A, SF2P nodes
- AI-driven digital flow certified for Samsung SF2P, with Hyper Cell and LLE 2.0
- Demonstrated analog IP migration from 4nm to 2nm process
- Joint RF/mmWave chip/package flow and 3D-IC power integrity analysis
- Targets AI data centers, ADAS/automotive, HPC, and RF connectivity markets
“By combining Cadence’s AI-driven design and silicon solutions with Samsung’s advanced processes, we’re delivering the technologies our mutual customers need to innovate and bring their products to market faster,” said Boyd Phelps, senior vice president and general manager, Silicon Solutions Group at Cadence.
