Meta detailed a major expansion of its open networking and hardware portfolio at the Open Compute Project (OCP) Global Summit 2025, revealing the next phase of its AI-scale data center architecture. The company outlined new disaggregated fabric designs, optical technologies, and open Ethernet collaborations aimed at powering the next generation of AI training clusters. Building on more than a decade of OCP engagement, Meta presented a roadmap that links open-source software, disaggregated hardware, and AI-centric networking into a unified fabric strategy. Key announcements included the evolution of the Disaggregated Scheduled Fabric (DSF), the debut of a new Non-Scheduled Fabric (NSF) architecture, the addition of Minipack3N based on NVIDIA Spectrum-4 switching silicon, and Meta’s leadership role in the newly established Ethernet for Scale-Up Networking (ESUN) initiative.
The dual-stage DSF marks a significant advancement in Ethernet-based AI interconnects. Originally introduced in 2024, the DSF uses a VOQ-based architecture compliant with the open OCP-SAI interface and Meta’s FBOSS network operating system. The new generation scales to support up to 18,432 XPUs, enabling non-blocking connectivity across an entire data center building. This fabric now acts as a core building block for AI superclusters that span multiple zones or even regions, supporting massive model training workloads with predictable latency and bandwidth. The two-stage DSF provides deterministic communication between thousands of GPUs and other accelerators, allowing Meta to design coherent-scale systems for its largest AI models.
In parallel, Meta introduced the Non-Scheduled Fabric (NSF), a new architecture designed for ultra-large AI clusters such as the Prometheus platform. NSF uses shallow-buffer Ethernet switches to achieve low round-trip latency while implementing adaptive routing for dynamic load balancing and congestion mitigation. This approach allows traffic to be distributed efficiently across the network without requiring pre-scheduled coordination, ensuring both high performance and resilience under demanding AI workloads. NSF complements DSF as a foundational technology for gigawatt-scale AI data centers, combining simplicity with scalability in open, disaggregated topologies.
On the hardware front, Meta expanded its open networking switch portfolio with the new Minipack3N system, a 51.2 Tbps platform co-developed with Accton and powered by the NVIDIA Spectrum-4 Ethernet ASIC. This switch joins Minipack3, which is based on Broadcom’s Tomahawk5, and Cisco’s 8501 built on Silicon One G200, giving Meta a diverse set of 51T OCP switches. Each model provides 64 OSFP ports for 800G connectivity, supports the OCP Switch Abstraction Interface (SAI), and runs the FBOSS software stack. The designs are power-efficient and retimer-free, optimizing for thermal management and energy consumption at hyperscale. These open switches serve as the backbone for both front-end and back-end fabrics across Meta’s data centers.
Meta also emphasized the evolution of its open network software stack. FBOSS, originally developed for Meta’s internal infrastructure, continues to mature with expanded support for OCP-SAI and new routing schemes optimized for DSF and NSF fabrics. Working with the OCP community and silicon vendors, Meta has extended SAI to enable features such as load-adaptive routing, VOQ management, and enhanced fault detection. These capabilities give operators and developers a consistent API for managing heterogeneous switch platforms while maintaining openness and interoperability.
Optical connectivity plays a critical role in this architecture. Meta announced several additions to its optics portfolio, including the new 2×400G FR4 LITE module for links up to 500 meters, optimized for intra–data center use where shorter reach and lower cost are key. This complements the previously deployed 2×400G FR4 BASE optics for 3-km spans. Together, these provide an efficient path for scaling 400G and 800G connections across Meta’s large-scale clusters. On the host and switch sides, Meta introduced 400G DR4 and 2×400G DR4 OSFP modules for direct NIC-to-switch connections, supporting AI workloads that demand the lowest possible latency.
Meta’s broader leadership in the OCP community was underscored by its role in founding the Ethernet for Scale-Up Networking (ESUN) initiative. Announced at OCP Summit 2025, ESUN brings together operators and vendors — including AMD, Arista, ARM, Broadcom, Cisco, HPE, Marvell, Meta, Microsoft, NVIDIA, OpenAI, and Oracle — to develop Ethernet standards for scale-up AI networking. The goal is to adapt Ethernet’s proven ecosystem to meet the stringent requirements of accelerator interconnects, focusing on lossless data transfer, adaptive error handling, and efficient multi-hop topologies. ESUN aligns with open standards organizations such as IEEE and the Ultra Ethernet Consortium to ensure that Ethernet continues to evolve as a viable technology for AI and HPC-scale fabrics.
“At Meta, we believe that open hardware is a catalyst for innovation,” the company said. “By collaborating within OCP, we are enabling a new era of scalable, efficient, and flexible AI infrastructure built on open standards.”
• Dual-Stage DSF delivers non-blocking interconnects for up to 18,432 XPUs across data center buildings
• NSF introduces adaptive, low-latency Ethernet fabrics for gigawatt-scale AI clusters
• Minipack3N adds NVIDIA Spectrum-4–based 51.2 Tbps switch to OCP’s open hardware lineup
• Expanded optics family adds 2×400G FR4 LITE and DR4 variants for cost-optimized AI interconnects
• Meta co-founds ESUN to advance Ethernet for large-scale AI and HPC networking
🌐 Analysis: Meta’s latest OCP contributions represent a decisive move toward open Ethernet-based fabrics for AI-scale networking, diverging from proprietary interconnect approaches. By expanding DSF and NSF architectures and collaborating through ESUN, Meta is pushing Ethernet into domains traditionally dominated by custom solutions. The alignment of hyperscalers and chipmakers around ESUN signals an industry-wide effort to unify Ethernet as a common foundation for AI infrastructure, paralleling developments in Ultra Ethernet and UALink.
