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Home » Inphi to acquire eSilicon for $226 million

Inphi to acquire eSilicon for $226 million

November 11, 2019
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Inphi Corporation agreed to acquire eSilicon for $216 million in both cash and the assumption of debt.

“The Inphi team is excited to enhance our value proposition to our cloud and telecom customers with the addition of the eSilicon team and IP,” said Ford Tamer, president and CEO of Inphi. “eSilicon adds to Inphi world-class 2.5D packaging, SerDes, custom silicon and operations teams. Just as we successfully leveraged our Cortina and Clariphy acquisitions, eSilicon will advance our shared commitments in driving successful customer engagement, industry-leading innovation, and best of class execution.”

Inphi lists the following drivers for the acquisition:

  • Combine Inphi’s DSP, TiA, Driver and SiPho disciplines with eSilicon’s 2.5D packaging and custom silicon design capabilities and accelerate the roadmap for electro-optics, 5nm advanced CMOS process node, and custom DSP solutions
  • Augment Inphi’s existing SerDes team and resources
  • Extend Inphi’s addressable market in Cloud data center networking and Telecom 5G infrastructure with top tier OEM customers
  • Expand Inphi’s presence into new, strategic geographies for talent acquisition with engineering design centers in Italy, Romania, Vietnam, and Spain and operations in Malaysia
  • Add between $80 to $120 million to 2020 revenue, be accretive to 2020 EPS and both the 2021 revenue and EPS growth rates
  • Increase Inphi’s operational scale with suppliers, lowering costs and resulting in financial leverage
  • Result in Inphi paying about 2.2X 2020 revenue in a combination of cash and debt assumption

The acquisition is expected to close in the fourth quarter of 2019, subject to US and Vietnamese regulatory approval and customary closing conditions. Concurrent with the signing of the definitive agreement, eSilicon has sold its Embedded Memory IP (SRAM, TCAM, and multi-port memory compiler) and Interface IP (HBM and HBI) assets to Synopsys Incorporated.

http://www.inphi.com

eSilicon tapes out 7nm Combo PHY for high bandwidth memory

Thursday, May 09, 2019  ESilicon  

eSilicon announced the tapeout of a 7nm test chip to provide silicon validation of its physical interface (PHY) to support the new JEDEC standard JESD235B, referred to informally as high bandwidth memory (HBM) 2E and emerging low-latency HBM technology.  The chip contains a 7nm PHY from eSilicon and a controller from Northwest Logic.  This 7nm test chip, along with a previously taped out 7nm test chip will be part of a 2.5D test system…

READ MORE

eSilicon Tapes Out 7nm 400G Gearbox/Retimer Test ASIC

Wednesday, May 01, 2019  ESilicon  

eSilicon announced the tapeout of a 7nm test ASIC that supports 400G gearbox and retimer functionality. Fabrication is expected in September. A gearbox converts multiple serial data streams at one rate to multiple streams at another rate. Serial-to-parallel and parallel-to-serial converters (SerDes) are critical to this functionality. A retimer improves signal integrity by equalizing, retiming and re-conditioning the received data to extend reach. The…

READ MORE

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