eSilicon announced the tapeout of a 7nm test chip to provide silicon validation of its physical interface (PHY) to support the new JEDEC standard JESD235B, referred to informally as high bandwidth memory (HBM) 2E and emerging low-latency HBM technology.
The chip contains a 7nm PHY from eSilicon and a controller from Northwest Logic. This 7nm test chip, along with a previously taped out 7nm test chip will be part of a 2.5D test system to verify end-to-end support for the new HBM interfaces. The PHY design is a “combo” device that supports HBM2, HBM2E and the emerging low-latency HBM interface in one physical IP block.
When compared to HBM2, the HBM2E standard increases total capacity from 8GB to 16GB, bandwidth per pin from 2.4 Gb/s to 3.2 Gb/s and bandwidth per stack from 307.2 GB/s to 410 GB/s. Samsung Electronics announced the industry’s first HBM2E to deliver the 3.2 Gb/s per-pin transfer speed, at NVIDIA’s GPU Technology Conference in March.
“HBM memory stacks are a critical component for many of our new FinFET-class 2.5D ASICs,” said Hugh Durdan, vice president, strategy and products at eSilicon. “We look forward to validating the performance and functionality of our combo PHY and Northwest Logic’s controller to support the latest HBM capabilities.”
