Integrated Device Technology (IDT) and Orange Silicon Valley have co-developed a new compute architecture that leverages massive, highly scalable, low-latency clusters of low-power NVIDIA Tegra K1 mobile processors along with using IDT’s RapidIO technology which can interconnect multiple nodes at up to 16 Gbps. The architecture can scale to more than 2,000 nodes in a rack and enables ultra-high Gflop density and energy efficiency not achievable with PCI Express or Ethernet technologies.
The design essentially interconnects a large number of low-power GPUs in a server rack, enableing tremendous computing horsepower with low latency and low energy consumption. It yields up to 23 Tflops per 1U server, or greater than 800 Tflops of computing per rack.
IDT said its new architecture matches computing cores with 16 Gbps data rate to each node for better computing-to-throughput balance, one of the key limitations in the industry today. The compute to I/O ratio will continue to improve with 40 Gbps IDT RapidIO 10xN technology.
The architecture allows for 60 nodes on a 19-inch 1U board, with more than 2,000 nodes in a rack. Any node can communicate with another node with only 400 ns of fabric latency. Memory-to-memory latency is less than two microseconds. Each node consists of a Tsi721 PCIe to RapidIO NIC and a Tegra K1 Mobile Processor with 384 Gflops per 16 Gbps of data rate, or 24 floating point operations per bit of I/O. This will be valuable at the rack level in data centers and at the individual analytics server level for wireless access networks.
The cluster was achieved with NVIDIA’s Jetson TK1 development kit, which is powered by the NVIDIA Tegra K1 mobile processor.
“Leading innovators in the ‘Big Data’ arena are increasingly discovering the benefits RapidIO interconnect can bring to their applications,” said Sean Fan, vice president and general manager of IDT’s Interface and Connectivity Division. “Our work with Orange Silicon Valley—connecting massive numbers of low-power NVIDIA mobile processors via RapidIO—demonstrates a breakthrough approach to addressing the tradeoffs between total computing, power and balanced networking interconnect to feed the processors.”
