Marvell introduced a custom AI accelerator (XPU) architecture featuring integrated Co-Packaged Optics (CPO) to enhance AI server performance. The new design supports higher bandwidth density and longer reach connections for AI server scaling, increasing XPU density from tens per rack with copper interconnects to hundreds across multiple racks using CPO. This technology offers improved data transfer rates and reduced latency, supporting next-generation AI infrastructure for cloud hyperscalers.
The custom AI accelerator architecture integrates Marvell’s 3D SiPho Engines with XPU compute silicon, high-bandwidth memory (HBM), and other chiplets on a single substrate. It uses high-speed SerDes, die-to-die interfaces, and advanced packaging to eliminate the need for copper cabling. Marvell’s CPO technology enables data transfer rates up to 100 times longer than traditional electrical cabling with enhanced power efficiency and minimal latency. The 6.4Tbps 3D SiPho Engine, which supports 200Gbps electrical and optical interfaces across 32 channels, offers twice the bandwidth and density while reducing power consumption per bit by 30%.
Marvell notes that its silicon photonics technology, deployed in its COLORZ data center interconnect modules for over eight years, has recorded more than 10 billion field hours. The company continues to expand its portfolio, including SerDes and die-to-die IP for custom XPUs, PCIe retimers, and a range of optical DSPs for data center interconnect applications. Multiple customers are evaluating the CPO technology for next-generation AI systems.
• Custom XPU design with Co-Packaged Optics (CPO) for AI servers
• XPU density increases from tens per rack to hundreds across multiple racks
• Integrated 3D SiPho Engine supports 6.4Tbps with 200Gbps electrical and optical interfaces
• Reduces power consumption per bit by 30% compared to 100G interfaces
• Silicon photonics technology field-tested for over 10 billion hours
“AI scale-up servers require connectivity with higher signaling speeds and longer distances to support unprecedented XPU cluster sizes,” said Nick Kucharewski, senior vice president and general manager of the Network Switching Business Unit at Marvell. “Integrating co-packaged optics into custom XPUs is the logical next step to scale performance with higher interconnect bandwidths and longer reach.”
“Silicon photonics is vital for scaling accelerated infrastructure connectivity to address increasing bandwidth demands, interconnect distances, power consumption, and total cost of ownership,” said Radha Nagarajan, senior vice president and chief technology officer of Optical Platforms at Marvell. “Since 2017, Marvell has pioneered the delivery of high-volume silicon photonics devices to top hyperscalers and leveraged this expertise to create a cutting-edge CPO architecture for the killer CPO use case of custom XPU connectivity.”
