Speaking to a packed audience at the AI Infrastructure Summit, Cadence AI Fellow Charles Alpert outlined how artificial intelligence is no longer just a workload but an essential tool for designing the chips, systems, and data centers that power it. His keynote, titled “Design for AI and AI for Design,” spotlighted the escalating power demands of hyperscale AI, the trillion-dollar infrastructure investment cycle, and the role of agentic AI in transforming design workflows.
Alpert said compute demand is doubling annually, with each generation of systems consuming 1.5–3x more power. Hyperscalers are already spending more than $300 billion a year on AI infrastructure, with long-term estimates between $5–8 trillion. This growth is forcing new approaches to 3D packaging, liquid cooling, and photonic integration—domains where Cadence is extending its EDA expertise into multiphysics simulation and digital twin modeling.
Cadence is also embedding AI directly into its tools. Optimization AI, already deployed in Cerebrus, has delivered over 1,000 tape-outs using reinforcement learning for physical design. The company now envisions “agentic AI” for design, where conversational interfaces and autonomous workflows can generate verification plans or RTL directly from specifications. Within three years, Cadence expects 90% of chips to be designed with AI-enabled flows.
• Compute demand for AI is doubling annually, driving data center power from megawatts to gigawatts
• Hyperscalers’ annual AI infrastructure spend exceeds $300B; long-term projections range from $5–8T
• Power use rising 1.5–3x per generation; cooling and packaging are major design bottlenecks
• 3D packaging is now deployed at scale, creating new verification and simulation challenges
• Liquid cooling and digital twins require multiphysics modeling across chips, systems, and facilities
• Cadence Integrity platform supports 3DIC and photonics design; simulation engines are being hardware-accelerated
• Cerebrus has delivered >1,000 tape-outs with reinforcement learning optimization
• Roadmap: conversational interfaces, agentic workflows, and RTL generation agents for verification
• By 2028, 90% of chips are expected to rely on AI-enabled Cadence design flows
“Our products have always been used to design chips, but with AI embedded into our systems, we’re seeing a reversal—AI is now accelerating the design process itself,” said Alpert.
🌐 Analysis: Cadence is advancing EDA beyond optimization into autonomous design, positioning “agentic AI” as the next layer of productivity for chip and system engineers. Rivals like Synopsys and Siemens EDA are also racing to integrate AI, but Cadence’s emphasis on multiphysics simulation—from 3D packaging to data center cooling—connects chip-level automation directly to hyperscale infrastructure challenges.
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