Alphawave Semi announced a significant advancement with the successful bring-up of its first chiplet-connectivity silicon platform utilizing TSMC’s 3nm process. This development introduces a Universal Chiplet Interconnect Express (UCIe) subsystem that enhances Alphawave Semi’s already strong portfolio in connectivity silicon, steering the industry towards a more cohesive and powerful chiplet ecosystem. This breakthrough aims to boost connectivity and computational capabilities, especially for high-performance AI systems.
Highlighting this achievement, Alphawave Semi showcased a live demonstration of their 24Gbps UCIe silicon platform on the TSMC 3nm process at the recent Chiplet Summit in Santa Clara, CA.
Key aspects of Alphawave Semi’s 3nm UCIe platform include:
- High Performance: The complete PHY + Controller subsystem supports data rates up to 24Gbps, offering high bandwidth density with minimal power consumption and latency. UCIe 1.1
- Compliance: Adherence to the latest UCIe Revision 1.1 Specification ensures compatibility and performance.
- Versatile Controller: Features a highly configurable Die-to-Die (D2D) controller that accommodates various protocols including PCIe/CXLTM, AXI-4, AXI-S, CXS, and CHI.
- Reliability Monitoring: Includes Bit Error Rate (BER) Health Monitoring for dependable operation.
- Advanced Packaging Compatibility: The PHY is designed to support TSMC’s sophisticated packaging technologies such as CoWoS and InFO, along with organic substrates for cost efficiency.
