Alphawave Semi has announced the successful tape-out of the industry’s first off-the-shelf multi-protocol I/O connectivity chiplet, utilizing TSMC’s 7nm process. The chiplet combines Alphawave Semi’s customizable connectivity IP, custom silicon, and advanced packaging capabilities. The 7nm multi-standard I/O chiplet boasts a comprehensive IP portfolio compliant with Ethernet, PCIe, CXL, and UCIe (Universal Chiplet Interconnect Express) Revision 1.1 standards.
The new chiplet delivers total bandwidth of up to 1.6 Tbps, supporting up to 16 lanes of multi-standard PHY with silicon-proven PCIe 6.0, CXL 3.x, and 800G Ethernet in various mixed operating modes. This development also lays the groundwork for a robust and open chiplet ecosystem, crucial for accelerating connectivity in high-performance AI systems through UCIe as a die-to-die connectivity subsystem. Alphawave Semi recently showcased an industry-first live demo of its 24 Gbps UCIe silicon platform at the Chiplet Summit 2024 in Santa Clara, CA.
Key Points:
- Advanced Capabilities: Integrates flexible and customizable connectivity IP, custom silicon, and advanced packaging.
- High Bandwidth: Delivers up to 1.6 Tbps total bandwidth, supporting 16 lanes of multi-standard PHY.
- Standards Compliance: Compliant with Ethernet, PCIe, CXL, and UCIe Revision 1.1 standards.
- AI System Connectivity: Enhances connectivity for high-performance AI systems using UCIe as a die-to-die connectivity subsystem.
- Live Demo: Showcased a 24 Gbps UCIe silicon platform at Chiplet Summit 2024.
- Customer Benefits: Offers flexibility and scalability for hyperscalers and datacenter infrastructure through mix-and-match high-performance custom SoCs.
- Collaboration with TSMC: Demonstrates the use of TSMC’s 3DFabric™ ecosystem to integrate advanced interfaces.
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