Alphawave Semi has completed the tape-out of its next-generation UCIe™ 3D chiplet IP on TSMC’s SoIC-X technology, part of the foundry’s 3DFabric® platform. This marks a significant step in advancing 3D integration for high-performance compute (HPC) and AI workloads. The new IP enables face-to-face (F2F) die stacking, providing up to 10x power efficiency and 5x signal density improvements compared to traditional 2.5D die-to-die interfaces.
The 3D architecture features a 5nm bottom die with through-silicon vias (TSVs) to support a 3nm top die, using Alphawave Semi’s proprietary 3DIO design methodology. This approach addresses critical bottlenecks in memory bandwidth and power delivery as monolithic SoC scaling slows. Alphawave’s work aligns with broader industry trends favoring disaggregated architectures and vertical integration via advanced packaging.
The announcement builds on a prior tape-out of UCIe IP on TSMC’s 2nm CoWoS® platform and supports the company’s roadmap to deliver UCIe with 64G support. Strategic collaboration with Siemens and TSMC reinforces Alphawave’s ecosystem positioning as a key enabler for chiplet-based AI and HPC systems.
- Delivers 10x power efficiency and 5x signal density over traditional 2.5D interfaces
- Supports F2F die stacking with 5nm-to-3nm TSV integration
- Built on TSMC’s SoIC-X 3DFabric advanced 3D packaging platform
- Part of Alphawave’s growing 3DIO IP portfolio for AI and HPC
- Collaborations announced with Siemens and TSMC under OIP program
- Builds on Alphawave’s 2nm UCIe IP tape-out on TSMC CoWoS® in June
- Future roadmap includes 64G UCIe support for next-gen chiplet systems
“This successful tape-out represents a significant milestone for Alphawave Semi and our AI platform,” said Mohit Gupta, EVP & GM at Alphawave Semi. “By combining our high-speed 3D UCIe IP with TSMC’s groundbreaking SoIC-X technology, we are directly addressing the memory and bandwidth bottlenecks that limit our customers’ next-generation AI and HPC applications.”
🌐 Analysis: The push toward UCIe-based chiplet systems has become a central theme in the race to scale AI infrastructure, especially as traditional monolithic SoC integration hits limits. Alphawave Semi’s latest achievement highlights the importance of TSMC’s 3DFabric technologies, which have gained traction among advanced silicon players. With partners like Intel, AMD, Broadcom, and NVIDIA also exploring UCIe, the ecosystem is rapidly coalescing around standardized 3D die integration, and Alphawave’s early leadership in IP positions it well for the next wave of modular compute.
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