AMD has achieved a key milestone by taping out and bringing up its next-generation EPYC processor, codenamed “Venice,” on TSMC’s 2nm (N2) node. The new chip becomes the first high-performance computing (HPC) product based on TSMC’s advanced N2 process, highlighting close engineering collaboration between AMD and TSMC. “Venice” remains on schedule for commercial launch in 2026, reinforcing AMD’s data center CPU roadmap.
In parallel, AMD completed bring-up and validation of its 5th Gen EPYC processors at TSMC’s Arizona Fab 21. The development underscores AMD’s investment in domestic semiconductor manufacturing and signals early production activity at the U.S.-based TSMC facility. This dual-track progress — leveraging both Taiwan’s cutting-edge N2 node and Arizona’s new fab — positions AMD for future capacity and resilience in supply chains.
TSMC’s N2 node introduces nanosheet transistor architecture for improved performance and power efficiency, aiming to support next-generation workloads in AI and cloud data centers. The success of the “Venice” silicon bring-up strengthens AMD’s position as a lead HPC customer across TSMC’s global manufacturing footprint.
- AMD “Venice” EPYC CPU is first HPC product on TSMC’s 2nm N2 process.
- Tape-out and bring-up of “Venice” achieved in collaboration with TSMC.
- Commercial launch of “Venice” expected in 2026.
- AMD completed bring-up of 5th Gen EPYC CPUs at TSMC Arizona Fab 21.
- TSMC’s N2 node uses nanosheet transistors for better power-performance scaling.
“We are working closely together to drive innovation and deliver the advanced technologies that will power the future of computing,” said Dr. Lisa Su, chair and CEO, AMD.
