Applied Materials introduced groundbreaking materials engineering innovations designed to enhance the performance-per-watt of computer systems. These innovations enable copper wiring to scale to the 2nm logic node and below, addressing the increasing demand for energy-efficient computing in the AI era.
The industry faces significant challenges as it scales to 2nm and below. Current logic chips, which contain billions of transistors connected by miles of microscopic copper wiring, rely on a combination of low-k dielectrics and copper to deliver performance and power-efficiency improvements. However, thinner dielectric materials at these scales make chips mechanically weaker, and narrower copper wires increase electrical resistance, potentially reducing performance and increasing power consumption. Applied’s new enhancements to its Black Diamond™ material address these issues by reducing the minimum k-value and increasing mechanical strength, essential for 3D logic and memory stacking.
Additionally, Applied Materials introduced its latest IMS (Integrated Materials Solution), combining six technologies in one high-vacuum system. This system includes a binary metal combination of ruthenium and cobalt (RuCo), which reduces the thickness of the liner and improves surface properties for void-free copper reflow, ultimately reducing electrical line resistance by up to 25%. This innovation, the Applied Endura Copper Barrier Seed IMS with Volta Ruthenium CVD, is being adopted by leading logic chipmakers and is set to enhance chip performance and power consumption significantly.
• Key Points:
• Materials Innovations : Applied Materials introduces enhancements to Black Diamond™ and a new IMS™ for advanced chip wiring and stacking.
• Enhanced Performance : Innovations enable copper wiring to scale to 2nm, reducing electrical resistance and improving power efficiency.
• Industry Adoption : Leading logic and DRAM chipmakers adopt Applied’s latest technologies, underscoring the company’s leadership in chip wiring processes.
Dr. Prabu Raja, President of the Semiconductor Products Group at Applied Materials, highlighted the importance of chip wiring and stacking in improving performance and power consumption. The new integrated materials solution from Applied allows for low-resistance copper wiring at emerging angstrom nodes, while a new low-k dielectric material reduces capacitance and strengthens chips for advanced 3D stacking.
“The AI era needs more energy-efficient computing, and chip wiring and stacking are critical to performance and power consumption,” said Dr. Prabu Raja , President of the Semiconductor Products Group at Applied Materials . “Applied’s newest integrated materials solution enables the industry to scale low-resistance copper wiring to the emerging angstrom nodes, while our latest low-k dielectric material simultaneously reduces capacitance and strengthens chips to take 3D stacking to new heights.”
