Arteris announced that Singapore-based 2V Systems has selected its Ncore 3 cache-coherent and FlexNoC 5 non-coherent interconnect IPs for a new IO chiplet designed for RISC-V–based data center SoCs. The collaboration targets high-bandwidth, low-latency data transport for AI workloads in multi-die system architectures.
The Arteris Network-on-Chip (NoC) IP serves as the data backbone for the 2V Systems IO chiplet, enabling efficient communication between heterogeneous compute chiplets while maintaining low power and scalability. The partnership reflects growing demand for modular, chiplet-based SoC designs that can handle the performance and energy constraints of AI infrastructure.
2V Systems plans to integrate Arteris’ multi-die interconnect technology into its next-generation server SoCs, aimed at cloud and AI data center deployments. These RISC-V–based designs are being developed by a team of former Intel, AMD, and Google engineers and focus on cost-effective, high-performance compute scalability.
- 2V Systems licensed Arteris Ncore 3 and FlexNoC 5 IP
- Target: Multi-die, RISC-V–based SoCs for AI and cloud data centers
- IO chiplet will serve as high-performance communication hub
- Enables low latency, low power data transport between heterogeneous dies
- Supports modular design and faster time-to-market for advanced SoCs
“The next generation of cutting-edge SoCs for AI and data centers will be built using IO chiplets to effectively scale compute,” said Aglaia Kong, CEO of 2V Systems. “Our multi-die SoCs will use Arteris Ncore IP and FlexNoC IP as the compute data transport across chiplets, meeting the high bandwidth, low latency, and low power needs of data centers and cloud infrastructure.”
🌐 Analysis: The 2V Systems partnership underscores Arteris’ momentum in multi-die and chiplet interconnect solutions, a growing focus area as AI workloads drive disaggregation in SoC architectures. Competitors such as Alphawave Semi, Synopsys, and Cadence are also expanding IP portfolios for chiplet interconnects, positioning to serve the next wave of RISC-V and AI accelerators.
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