Banias Labs achieved first-pass silicon success for its optical DSP SoC using Synopsys 112G Ethernet PHY IP and EDA Design Suite.
Synopsys provided Banias Labs with a comprehensive IP solution that included a routing feasibility study, packaging substrate guidelines, signal and power integrity models, and thorough crosstalk analysis. In addition, Banias leveraged Synopsys’ EDA Design Suite to deliver high quality of results with optimized power, performance, area and yield.
“Today’s high-performance computing infrastructure requires trusted and complete solutions for high-end design,” said Amnon Rom, CEO at Banias Labs. “Using Synopsys EDA Design Suite to integrate Synopsys Ethernet PHY IP with custom features and capabilities into our chip offered the solutions we needed to boost system performance and accelerate our time-to-market.”
“Implementing ultra-high-speed Ethernet designs comes with significant power, area, packaging, and signal integrity challenges,” said John Koeter, senior vice president of marketing and strategy for IP at Synopsys. “Synopsys provides companies like Banias Labs with high-performance, low-latency solutions that enable hyperscale data center, networking, AI, optical module and Ethernet switch SoCs for emerging high-performance computing designs.”
The Synopsys 112G Ethernet PHY IP is available in multiple advanced process technologies to 3nm.
