Cadence Design Systems has optimized its chip design software for Samsung Foundry’s advanced-process technologies down to 4nm.
The companies said Cadence digital 20.1 flow provides capabilities that are well-suited for Samsung Foundry’s advanced-process technologies. For example, the iSpatial technology allows a seamless transition from the Genus Synthesis Solution to the Innovus Implementation System using a common user interface and database. Machine learning (ML) capabilities enable users to leverage their existing designs to train the GigaOpt optimization technology to minimize design margins versus traditional place-and-route flows.
“With the ongoing innovation in hyperscale computing and autonomous driving, there is ever-increasing demand for HPC capacity,” said Sangyun Kim, vice president of the Foundry Design Technology Team, at Samsung Electronics. “By combining the latest Samsung Foundry advanced-process nodes with the Cadence 20.1 digital full flow, our customers can achieve their design goals quickly and efficiently.”
“The newly optimized Cadence digital flow makes it much simpler for customers to achieve PPA targets using Samsung Foundry’s advanced-process technologies,” said Michael Jackson, corporate vice president, R&D in the Digital & Signoff Group at Cadence. “By expanding upon our longstanding collaboration with Samsung Foundry, designers can rapidly adopt Samsung Foundry’s validated HPC methodologies to deliver exceptional silicon performance on time.”
http://www.cadence.com/go/advnodes
