Cadence announced a major expansion of its collaboration with TSMC to accelerate AI and HPC semiconductor design, covering advanced EDA flows, 3D-IC packaging, and high-performance IP. The partnership spans process nodes from N3 to N2 and A16, with early work already underway for TSMC’s A14 process. The companies said these updates will streamline time-to-market for customers deploying AI-driven design methodologies.
Cadence confirmed that its AI-enabled design tools, including the JedAI platform, Cerebrus Intelligent Chip Explorer, and Innovus+ AI Assistant, are validated for TSMC’s N2 process. These flows bring automation for DRC violation fixing and improved power, performance, and area optimization. On the 3D-IC side, Cadence tools now support TSMC’s 3DFabric packaging ecosystem, adding automation for bump connections, chiplet placement, and thermal simulation techniques tied to the TSMC Compact Universal Photonic Engine (TSMC-COUPE).
On the IP front, Cadence introduced silicon-proven offerings on TSMC N3P, including the first HBM4 IP, high-speed LPDDR6/5X and DDR5 MRDIMM Gen2 memory interfaces, PCIe 7.0 at 128GT/s, a 224G SerDes, eUSB2V2, and 32G UCIe IP. These solutions target bandwidth and interconnect challenges for next-generation AI infrastructure and chiplet ecosystems.
• Cadence AI design flows validated for TSMC N3, N2, and A16, with A14 PDK due later this year
• AI-driven automation improves productivity for N2 node chip design
• 3D-IC tools enhanced for TSMC 3DFabric, including chiplet and photonic integration support
• New IP on N3P includes HBM4, LPDDR6/5X, DDR5 MRDIMM Gen2, PCIe 7.0, 224G SerDes, UCIe 32G, and eUSB2V2
• Focus on AI, HPC, and emerging AI PC workloads
“Cadence and TSMC remain committed to speeding up and improving the design process for advanced silicon for our customers,” said Chin-Chi Teng, senior vice president and general manager of the Digital and Signoff Group at Cadence.
🌐 Analysis: Cadence’s deepened integration with TSMC underscores the growing importance of AI-driven design tools and chiplet-based architectures in AI infrastructure. The addition of validated flows at N2 and silicon-proven IP at N3P positions Cadence strongly against rivals Synopsys and Siemens, who are also racing to enable design automation and IP for AI workloads. The extension of work into TSMC’s A14 process indicates both firms’ urgency in preparing the design ecosystem ahead of customer tapeouts in the coming technology nodes.
🌐 We’re tracking the latest developments in networking silicon. Follow our ongoing coverage at: https://convergedigest.com/category/semiconductors/
