Cadence Design Systems introduced its Janus Network-on-Chip (NoC) technology for managing data delivery between silicon components in complex SoCs and disaggregated multi-chip systems. The Cadence Janus NoC manages these simultaneous high-speed communications efficiently with minimal latency, enabling customers to achieve their PPA targets faster and with lower risk.
The Cadence Janus NoC leverages Cadence’s trusted Tensilica RTL generation tools and extensive software and hardware portfolio for simulation, emulation, and performance analysis. This flow enables architectural exploration, resulting in the best NoC design for product needs.
The Cadence Janus NoC addresses the routing congestion and timing issues common in complex SoC interconnects, often only apparent during physical implementation. As a first-generation NoC, it provides a platform for future innovations, including support for industry-standard memory and I/O coherence protocols.
Highlights
- Cadence’s GUI enables NoC configuration ranging from small subsystems to full SoCs and future multi-chip systems.
- PPA-optimized RTL enables SoC designers to achieve their bandwidth and latency goals.
- Packetized messages enable higher utilization of wires, reducing wire count and timing closure challenges.
- The NoC’s built-in power management, clock domain crossing and width matching reduce design complexity.
- Cadence’s extensive simulation and emulation capabilities enable early architectural exploration, allowing quick validation of PPA results to ensure the configuration meets design requirements.
- Customers can design a subsystem and reuse it in a full SoC context of the NoC, allowing future reuse in a multi-chip system.
- The NoC is compatible with any IP with an industry-standard interface, including AXI4 and AHB.
“Cadence is an established leader in IP and design quality, and we continue to invest in our foundational interface and processor IP, system IP, software and design services capabilities to enable our customers to develop differentiated and disaggregated designs,” said Boyd Phelps, senior vice president and general manager of the Silicon Solutions Group at Cadence. “The addition of the Cadence Janus NoC to our growing system IP portfolio is a key milestone in this strategy. Our evolution from an IP provider to an SoC design partner delivers greater value to our customers, empowering them to focus valuable engineering resources on differentiating their silicon.”
