Intel Foundry Services (IFS) and Cadence Design Systems entered into a multiyear strategic agreement to jointly develop a portfolio of key customized IP, optimized design flows and techniques for Intel 18A technology featuring RibbonFET gate-all-around transistors and PowerVia backside power delivery.
This will enable joint customers to accelerate their SoC project schedules on process nodes from Intel 18A and beyond while optimizing for performance, power, area, bandwidth and latency for demanding AI, HPC and premium mobile applications.
Fast-growing market segments, such as AI/ML, HPC and premium mobile computing, require the latest standards in IP to take advantage of advanced packaging and silicon process technologies. Cadence’s leading-edge implementations of trailblazing standards, such as advanced memory protocols, PCI Express, UCI Express and others for these key segments, enable joint customers to achieve scalable, high-performance designs that accelerate their time to market in IFS’ most advanced silicon technologies and 3D-IC packaging capabilities.
“We furthered our partnership with Intel Foundry Services through a significant strategic multiyear agreement to provide design software and leading IP at multiple Intel advanced nodes, thereby advancing Intel’s IDM 2.0 strategy and accelerating mutual customer success,” said Anirudh Devgan, president and chief executive officer at Cadence.
“We’re very excited to expand our partnership with Cadence to grow the IP ecosystem for IFS and provide choice for customers,” said Stuart Pann, Intel senior vice president and general manager of IFS. “We will leverage Cadence’s world-class portfolio of leading IP and advanced design solutions to enable our customers to deliver high-volume, high-performance and power-efficient SoCs on Intel’s leading-edge process technologies.”
