Cadence introduced a new category of AI silicon with the launch of the Tensilica NeuroEdge 130 AI Co-Processor (AICP), designed to complement NPUs and offload non-MAC AI tasks such as ReLU, sigmoid, and tanh. Targeting automotive, industrial, consumer, and mobile SoCs, the new processor offers more than 30% area savings and over 20% lower dynamic power consumption compared to existing DSPs, without sacrificing performance. The NeuroEdge 130 AICP is based on Cadence’s proven Vision DSP architecture and is supported by the NeuroWeave SDK for rapid model deployment.
With its VLIW-based SIMD architecture, optimized ISA, and future-ready programmability, the AICP delivers a flexible platform to handle pre- and post-processing layers not suited to NPUs. The processor supports both in-house and third-party NPU IPs, ensuring broad compatibility. Cadence positioned the AICP as a key component in next-gen edge AI systems, enabling execution of multimodal and LLM-based agentic AI models with lower latency and power. The processor is ISO 26262-ready for safety-critical automotive deployments and has already garnered strong customer interest.
Early endorsements came from indie Semiconductor, MulticoreWare, and Neuchips, all of whom cited the AICP’s efficiency and adaptability for ADAS, edge vision, and AI data center use cases. The processor’s lightweight AI library and compatibility with the TVM stack allow developers to optimize workloads while minimizing compiler overheads.
- New AI co-processor class for pre/post-NPU task offloading.
- 30% area savings, 20% dynamic power reduction vs. Vision DSPs.
- Compatible with Cadence Neo NPUs and third-party NPU IPs.
- Optimized for agentic and physical AI tasks like robotics, ADAS, healthcare.
- Supported by Cadence’s NeuroWeave SDK and standalone AI library.
- ISO 26262-ready and available now for integration in AI SoCs.
“Our customers asked for a small, efficient AI co-processor to future-proof their AI systems. The NeuroEdge 130 AICP meets that challenge head-on with leading performance and power efficiency,” said Boyd Phelps, SVP and GM of Cadence’s Silicon Solutions Group.
