Cavium Networks unveiled its next generation NITROX DPI II family of L7 content processors offering deep packet inspection across millions of definable rules at 40 Gbps.
The NITROX DPI II is a “bump-in–the-wire” single chip deep packet inspection processor designed for a range of enterprise, data center, and 3G/4G infrastructure equipment requiring fine grain content processing at wire speed. DPI processing enables advanced functions, such as protocol analysis, application recognition, intrusion prevention, anti-malware protection, URL Filtering, unified threat management, antivirus gateways, subscriber charging, application aware QOS and service level agreements, usage monitoring and preventing denial of service.
The new NITROX DPI II chip is enabled by Cavium’s Hyper Finite Automata (HFA) engines and optimized TurboDPI software. It can be used in both inline and coprocessor modes. In coprocessor mode it connects over its in-built PCI Express interface to offload general purpose processors i.e. x86, MIPs or PowerPC based systems that lack such advanced hardware DPI engines.
The HFA engines in CN18XX family support highly complex rules and can process millions of rules without any performance impact. The NITROX DPI II family is fully software and rule syntax compatible with the DPI engines in Cavium’s OCTEON II processor family and the NITROX DPI CN17XX family offering a wide variety of scalable and compatible system design options to customers.
“Our new NITROX DPI II product line further extends our reach into ‘bump-in-the-wire’ and coprocessor designs where power, space and real estate budget previously limited the ability to add complex deep packet inspection features,” said Rajneesh Gaur, GM of the Coprocessors & Adapters Group, Cavium Networks. “Now OEMS building switches, routers and WAN appliances can more easily add DPI functionality.”http://www.caviumnetworks.com
