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Home » Chip-Level Voltage Regulation from Marvell Targets AI Power Bottlenecks

Chip-Level Voltage Regulation from Marvell Targets AI Power Bottlenecks

June 17, 2025
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Marvell introduced a new Package Integrated Voltage Regulator (PIVR) solution designed to significantly improve power delivery for high-performance computing platforms in AI and cloud infrastructure. The PIVR technology marks a shift from traditional board-level power architectures toward integrated, chip-level solutions that reduce power loss and increase current density. Targeting custom XPUs and multi-kilowatt compute engines, Marvell’s pre-validated PIVR delivers up to 2x higher current density and up to 85% lower transmission losses in final-stage voltage conversion.

The compact architecture moves voltage regulation closer to the processor, saving board space and allowing more efficient, dynamic voltage scaling. With current densities reaching 3–4 amperes per mm², PIVR enables denser compute configurations and better thermal and cost efficiency. This innovation is essential for hyperscalers building next-generation AI clusters that require tightly coupled power and processing to meet performance and ROI goals. Marvell is collaborating with a wide ecosystem of power delivery partners—including Infineon, MPS, Empower Semiconductor, Endura, Ferric, and Photeon—to accelerate industry adoption.

The PIVR solution is the latest addition to Marvell’s custom silicon platform, which integrates proprietary IP in areas like PCIe Gen 7, co-packaged optics, die-to-die interconnects, custom HBM, and silicon photonics. By delivering validated power subsystems optimized for AI workloads, Marvell aims to overcome power bottlenecks and enable vertical integration strategies that match the escalating compute needs of hyperscale environments.

  • Marvell PIVR delivers up to 85% transmission loss reduction and 2x higher current density
  • Enables 4kW-class compute platforms for hyperscale AI and cloud
  • Integrated at package level for tighter coupling, lower cost, and improved efficiency
  • Supports dynamic voltage scaling and power tuning in real-time
  • Backed by partners including Infineon, MPS, Empower, Endura, Ferric, and Photeon

“Placing IVR under, near, or inside the package delivers greater performance and greater efficiency at the same time—an extremely challenging feat—while giving cloud operators greater flexibility,” said Will Chu, senior vice president and general manager of Custom Cloud Solutions at Marvell.

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Jim Carroll

Jim Carroll

Editor and Publisher, Converge! Network Digest, Optical Networks Daily - Covering the full stack of network convergence from Silicon Valley

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