Credo announced the production availability of a low-power 3.2Tbps retimer XSR-enabled high-speed connectivity chiplet with 112Gbps lane rates.
Credo’s new Nutcracker new device, which is optimized for multi-chip-modules (MCM) ASICs, has 32 low-power lanes of 112G XSR SerDes on the host side, which communicate with the in-module system-on-chip (SOC) core ASIC. The chiplet has 32 lanes of low-power 112G MR+ reach-optimized DSP to provide the off-module interface on the line side.
The company says its unique DSP technology allowed the development of the low-power 32x112Gbps XSR to 32x112Gbps MR+ retimer die in TSMC’s 12nm process. In contrast, alternative solutions will require the usage of more costly 7nm or 5nm nodes.
“We developed and commercialized Nutcracker in a strategic collaboration with a large, Fortune 200 customer,” said Jeff Twombly, Vice President of Business Development at Credo. “Nutcracker is now the leading solution for next-generation ASIC deployments requiring heterogeneous MCM approaches to achieve the performance scale demanded across all technology industries, including emerging co-packaged optics in the data center,” Twombly continued.
