Credo introduced its 112G PAM4 SerDes Intellectual Property (IP) family on TSMC’s N5 and N4 process technologies. Credo’s IP supports a wide range of demands including long reach plus (LR+), long reach (LR), medium reach (MR), extreme short reach plus (XSR+), and extreme short reach (XSR), – required by applications including compute, switching, AI, machine learning, security, and optical deployments.
Credo says uts unique software programmable innovations allow architects to optimize power and performance on a lane-by-lane basis, unleashing new levels of system level performance. These new 112G PAM4 SerDes IP were designed to meet the ever-growing data needs of high-speed, data-intensive applications and early access design customers can engage immediately by contacting the Credo sales team. Production, silicon validation, design kit of these 112G SerDes for multiple TSMC processes from N16 to N4 are available on TSMC-Online.
Jim Bartenslager, Associate Vice President of Business Development for IP Products commented, “Credo’s advanced mixed signal and DSP 112G PAM4 SerDes architectures were developed and proven on the TSMC 12nm process technology for Credo’s complete family of connectivity solutions for both copper and optical applications. We have ported our unique, purpose-built SerDes technology to the TSMC N5 and N4 processes to allow our partners and customers to seamlessly integrate our industry leading 112G PAM4 IP into larger scale monolithic and multi-chip-module ASICs.”
“Our latest collaboration with Credo makes it easy for customers to benefit from the significant power and performance improvements of TSMC’s advanced N5 and N4 processes,” said Dan Kochpatcharin, Director of the Design Infrastructure Management Division at TSMC. “We look forward to working closely with Credo to address the design challenges for rapid advancement of applications in compute, switching, AI, and machine learning.”
