The CXL Consortium, which was formed in 2019 to develop an open industry standard group for high-speed CPU interconnect, announced the release of the CXL 2.0 specification.
CXL is an open industry-standard interconnect offering coherency and memory semantics using high-bandwidth, low-latency connectivity between host processor and devices such as accelerators, memory buffers, and smart I/O devices. The CXL 2.0 specification adds support for switching for fan-out to connect to more devices; memory pooling for increased memory utilization efficiency and providing memory capacity on demand; and support for persistent memory – all while preserving industry investments by supporting full backwards compatibility with CXL 1.1 and 1.0.
Key Highlights of the CXL 2.0 Specification:
- Adds support for switching to enable device fan-out, memory scaling, expansion and the migration of resources.
- Includes memory pooling support to maximize memory utilization, limiting or eliminating the need to overprovision memory.
- Introduces standardized fabric manager specification for inventory and resource allocation to enable easier adoption and management of CXL-based switch and fabric solutions.
- Provides standardized management of the persistent memory interface and enables simultaneous operation alongside DDR, freeing up DDR for other uses.
- Introduces managed hot-plug support to take a CXL device online or offline from the system.
- Adds link-level Integrity and Data Encryption (CXL IDE) to provide confidentiality, integrity and replay protection for data transiting the CXL link.
- Supports a wide variety of industry interconnect form factors and standardized management interfaces to ease implementation.
- Includes Compliance and Interoperability specifications and in-system testing to enable a robust and interoperable multi-vendor ecosystem.
Compute Express Link (CXL) promises high-speed CPU interconnect
Alibaba, Cisco, Dell EMC, Facebook, Google, Hewlett Packard Enterprise, Huawei, Intel and Microsoft have teamed up to form Compute Express Link (CXL), an open industry standard group for high-speed CPU interconnect.
CXL will maintain memory coherency between the CPU memory space and memory on attached devices, which allows resource sharing for higher performance, reduced software stack complexity, and lower overall system cost. The technology is built upon PCI Express (PCIe) infrastructure, leveraging the PCIe 5.0 physical and electrical interface to provide advanced protocol in three key areas:
- I/O Protocol
- Memory Protocol, initially allowing a host to share memory with an accelerator
- Coherency Interface
The group has completed work on a CXL Specification 1.0 for interconnect between the CPU and platform enhancements and workload accelerators, such as GPUs, FPGAs and other purpose-built accelerator solutions.
