eSilicon plans to demonstrate the silicon performance of its 7nm 56G long-reach SerDes during ECOC 2018 (Anritsu booth #408).
eSilicon will show a periodic pattern generator (PPG)-to-chip live demo with different backplane reaches. Specifically, the demonstration will show 56G PAM4 data transfer running at 56Gb/s over two different BERTSCOPE channels with two different reaches, both driven by the Anritsu MP1900A Signal Quality Analyzer-R using a passive and an active PAM4 combiner. The demo with Anritsu is significant because it will show how it is possible to leverage TX finite impulse response (FIR) capabilities to increase performance and improve power figure of merit (FOM) and functionality. A key feature is high insertion loss tolerance with low bit-error rates to support increased bandwidth in legacy equipment.
“To obtain such reach and effectively stress the PAM4 SerDes receiver, it is very important to be able to generate an original extremely high-quality signal, and include equalization and stress tools for full control of the TX side. During the bring-up period, a flexible solution like Anritsu’s MP1900A is the best choice for an interoperability test,” said Anritsu EMEA Wireline Marketing Director Alessandro Messina.
