eSilicon announced the tapeout of a 7nm test ASIC that supports 400G gearbox and retimer functionality. Fabrication is expected in September.
A gearbox converts multiple serial data streams at one rate to multiple streams at another rate. Serial-to-parallel and parallel-to-serial converters (SerDes) are critical to this functionality. A retimer improves signal integrity by equalizing, retiming and re-conditioning the received data to extend reach.
The test ASIC includes four lanes of eSilicon’s long-reach 112 Gbps SerDes and eight lanes of its long-reach 56 Gbps SerDes. The eSilicon SerDes IP is integrated with media access control (MAC), forward error correction (FEC) and gearbox IP from Precise-ITC. The test ASIC is designed to allow customers to evaluate eSilicon’s SerDes IP and the Precise E-pak Ethernet IP in a test vehicle that is representative of a real-life application. It features long reach and low power as well as low latency for time-critical applications, such as high-performance computing. The technology in the chip can be used as the basis for developing 400G and 800G systems.
“This new test ASIC will open up new opportunities for our customers,” said Hugh Durdan, vice president, strategy and products at eSilicon. “We employed the latest release of our StarDesignerä 7nm flow for this design. Thanks to the global, early analysis of integration challenges delivered by the flow, we were able to meet all performance parameters for this design and tape out on schedule.”
