Experts from Meta, Cisco, NVIDIA, and the global Ethernet ecosystem gather December 2–3 in Mountain View to examine 400G signaling and the technologies shaping Ethernet’s AI era.
The Ethernet Alliance is bringing a deep bench of technical leaders to TEF 2025: Ethernet for AI, set for December 2–3 at the Hyatt Centric in Mountain View. The two-day forum centers on how Ethernet must adapt as AI workloads scale, with IEEE P802.3dj and emerging 400G/lane signaling poised to influence future AI data center design. With chipmakers, hyperscalers, and system vendors represented on stage, the event provides a real-time look at how the Ethernet ecosystem is aligning around the next decade of AI infrastructure.
The agenda spans 400Gb/s electrical and optical signaling, SerDes evolution, system design implications for AI clusters, and interoperability advances such as CMIS. Speakers from Meta, Cisco, Arista, NVIDIA, Keysight, Lightmatter, MediaTek, Broadcom, Ciena, OIF and others will dissect the performance, latency, and manageability requirements that define Ethernet’s role in large-scale AI networks. The event also offers early access to the Ethernet Alliance’s 2026 Ethernet Roadmap, mapping the path from 400G/lane technologies toward 3.2 TbE.
Platinum sponsors Cisco and Huawei, along with a wide roster of ecosystem supporters, underscore industry momentum around high-bandwidth Ethernet architectures. “Cisco’s participation in TEF 2025 allows us to engage with and learn from other industry leaders and work together on solutions that will shape the next decade of Ethernet and AI integration,” said Sai Gopalakrishnan, senior director, technical marketing, Provider Connectivity Group, Cisco.
TEF 2025: Ethernet for AI – Full Agenda and Speaker Lineup
Featured Keynote
• Transitioning to 400G SerDes: Key Drivers and System Design Implications for Future AI Workloads – Halil Cirit, AI interconnect architect, Meta
Cirit will examine how 400G SerDes impacts performance, scalability, and system design for next-generation AI deployments.
Select Panel Sessions
400Gb/s Signaling for AI Networks From a System Perspective
• Moderator: Alan Weckel, co-founder and technology analyst, 650 Group
• Panelists: Gary Nicholl, Brian Welch (Cisco Systems, Inc.); Arihant Jain (Arista Networks)
Discussion includes how CMIS enables interoperability and how scale-out AI architectures influence interconnect strategies.
400Gb/s Electrical Signaling for AI Networks
• Moderator: Lisa Huff, DC Tech Analysis
• Panelists: Hadrien Louchet (Keysight Technologies, Inc.); Jim Hsieh (MediaTek Inc.); Bijan Nowroozi(Lightmatter, Inc.)
Focus on channel modeling, signal generation, and modular interconnect design that accelerate 400Gb/s per-lane electrical signaling.
Ethernet for AI Isn’t Just Evolving – It’s Exploding
• Presenter: John D’Ambrosia, Futurewei Technologies
Examining electrical and optical signaling advances defining 400Gb/s Ethernet and the roadmap toward 3.2 Tb/s Ethernet.
Additional Speakers From:
Altera (Intel), Alphawave Semi, Amphenol, Broadcom, Ciena, Dell’Oro Group, Huawei, LightCounting, Molex, NVIDIA, OIF, Panduit, RANOVUS, TE Connectivity.
Sponsors:
Platinum sponsors Cisco and Huawei; additional support from Amphenol, Ciena, 650 Group, IWCS, CCCA, Dell’Oro Group, LightCounting, OIF, SNIA, and Ultra Ethernet Consortium (UEC).
2026 Ethernet Roadmap
Attendees will receive early access and printed copies of the 2026 Ethernet Roadmap, outlining standards evolution and commercial pathways from today’s 400G/lane efforts toward future 3.2 TbE architectures spanning optics, copper, PHYs, and AI-scale designs.
“Huawei’s continued involvement with TEF reflects our belief in its vital role as a catalyst for the Ethernet ecosystem. By fostering collaboration and insight-sharing, TEF helps steer the industry toward the next generation of Ethernet needed to power the AI era,” said Xiaolong Zheng, director of research, Huawei Datacom Product Line.
More information is posted here: https://ethernetalliance.org/tef-2025-ethernet-for-ai/
🌐 Analysis
TEF 2025 arrives as the industry pushes toward 400G/lane signaling to support AI cluster sizes measured in tens of thousands of accelerators. The forum brings together key technical leaders behind IEEE P802.3dj, CMIS, Ultra Ethernet, and emerging SerDes architectures—areas where interoperability and multi-vendor maturity remain top priorities. The agenda reflects strong momentum around Ethernet-based fabrics for AI scale-out, with hyperscalers and silicon vendors evaluating paths to 800G, 1.6T, and ultimately 3.2T signaling. This year’s inclusion of Meta, NVIDIA, Cisco, and a broad set of PHY, optics, and interconnect specialists highlights how Ethernet is positioning itself as a primary transport for AI clusters into 2026.
🌐 We’re tracking the latest developments in AI infrastructure and data-center networking. Follow our ongoing coverage at: https://convergedigest.com/category/ai-infrastructure/
