Arm, Cadence Design Systems, and Xilinx introduced a development platform cloud-to-edge infrastructure based on the new Arm Neoverse N1.
The Neoverse N1 System Development Platform (SDP) is based on TSMC’s 7nm FinFET process technology and is also the industry’s first 7nm infrastructure development platform enabling asymmetrical compute acceleration via the CCIX interconnect architecture/
The joint solution is available to hardware and software developers for hardware prototyping, software development, system validation, and performance profiling/tuning. It includes Cadence IP for CCIX, PCI Express (PCIe) Gen 4 and DDR4 PHY IP.
The SDP includes a Neoverse N1-based SoC with an operating frequency of up to 3GHz, full-sized caches and generous amounts of memory bandwidth with the latest optimized system IP. The robustness of the SDP is ideal for development, debug, performance optimization and workload analysis on a wide range of applications including those for machine learning (ML), artificial intelligence (AI) and data analytics.
“The new Neoverse platforms deliver the performance and efficiency required to enable the cloud-to-edge infrastructure for a world with a trillion connected devices. Our ongoing SDP collaboration with Cadence, TSMC, and Xilinx truly enables developers with the system development tools necessary to innovate and deliver optimized Neoverse-based designs,” stated Drew Henry, senior vice president and general manager, Infrastructure Line of Business, Arm.
