Global Unichip Corp. (GUC) and Ayar Labs formed a new partnership to integrate co-packaged optics (CPO) into GUC’s advanced ASIC design services, aiming to support the optical I/O requirements of next-generation AI, HPC, and cloud networks. The companies are co-developing an XPU multi-chip package (MCP) that brings Ayar Labs’ TeraPHY optical engines directly onto the organic substrate, enabling optical links where conventional electrical signaling hits performance and power ceilings.
The new architecture targets more than 100 Tbps of full-duplex bandwidth from a single XPU package—an order-of-magnitude jump over today’s leading devices. The design includes UCIe-S (64 Gbps) connectivity between optical engines and I/O chiplets and UCIe-A (64 Gbps) links from I/O chiplets to the main AI die over local silicon interconnect (LSI) bridges. The joint team is also tackling package-level power integrity, thermal management, mechanical stress, and warpage challenges to make CPO a production-ready option for hyperscale deployments.
GUC plans to share technical details at the 2025 TSMC Open Innovation Platform Ecosystem Forum on November 18 in Hsinchu. The project leverages GUC’s advanced packaging flows and TSMC’s process ecosystem, combined with Ayar Labs’ silicon photonics roadmap, to explore CPO designs suitable for large-scale AI and data-center scale-up architectures.
• XPU MCP incorporates Ayar Labs’ TeraPHY optical engines directly onto the organic substrate
• >100 Tbps full-duplex optical bandwidth target from a single package
• UCIe-S (64 Gbps) for optical engine ↔ I/O chiplet connections
• UCIe-A (64 Gbps) for I/O chiplet ↔ AI die connections over LSI bridges
• Package-level thermal optimization and new stiffener design enabling detachable fiber coupling
• Focus areas include signal integrity, power delivery, mechanical stress, and scaling for hyperscalers
• GUC to detail advancements at the 2025 TSMC OIP Forum in Hsinchu
“Our new joint design allows us to address the challenges of CPO integration – architectural, power and signal integrity, mechanical and thermal – ensuring our future customers have access to a robust, high-bandwidth and power-efficient solution,” said Igor Elkanovich, CTO of GUC.
🌐 Analysis
The GUC–Ayar Labs partnership marks a significant alignment between a top-tier advanced ASIC design house and one of the industry’s earliest and most persistent champions of monolithic silicon photonics for optical I/O. As hyperscale AI clusters push electrical interfaces toward irrecoverable limits in reach, bandwidth density, and power consumption, both companies are positioning themselves to define how co-packaged optics (CPO) will be engineered into production AI silicon over the next several process nodes.
Founded in 1998 and majority-owned by TSMC (35%), GUC has evolved from a physical design service provider into one of the world’s most sophisticated ASIC integrators. The company’s core value comes from its deep access to TSMC’s leading-edge nodes and its ability to combine large dies, chiplets, and advanced packaging—including CoWoS, InFO, and 2.5D/3D IC technologies—into turnkey SoC programs. GUC’s customer base increasingly consists of hyperscalers and AI infrastructure providers building custom accelerators, XPUs, network processors, and memory-rich compute architectures. By moving optical engines directly into its multi-chip package playbook, GUC aims to offer hyperscalers a viable on-ramp to CPO without having to build full photonics/IPD supply chains themselves.
Ayar Labs, founded in 2015 out of research at MIT, UC Berkeley, and Stanford, has long pursued a monolithic approach to integrating lasers, modulators, detectors, and wavelength multiplexing on a CMOS-compatible silicon photonics platform. Its TeraPHY optical I/O chiplet is designed to replace entire banks of electrical SerDes with wavelength-multiplexed optical interfaces that deliver high bandwidth density at dramatically lower picojoules per bit. The technology is based on microring modulators, heterogeneously integrated lasers, and WDM architectures that can scale to tens of wavelengths per fiber, enabling terabit-class links with extremely low power draw. Ayar Labs has also been a central contributor to open optical I/O standardization efforts, collaborating with major silicon, packaging, and fiber connector ecosystem players.
Technologically, the announcement touches on several fundamental challenges that have slowed CPO adoption for the past decade:
• Thermal coexistence of lasers and hot compute dies – The XPU package combines optical engines, I/O chiplets, and a large AI die. Co-packaging requires aggressive thermal optimization, stiffener design, and airflow/heat-spreader engineering so that optical components remain in their safe operating envelope even as the main die operates at >500 W.
• Power delivery for dense multi-wavelength engines – Optical modulators and WDM drivers introduce new current and noise profiles into the package. Addressing power integrity (PI) is key to maintaining signal linearity and energy efficiency.
• Signal integrity at chiplet boundaries – The use of both UCIe-S and UCIe-A for communication between optical engines, I/O chiplets, and the main compute die reflects the growing role of standardized chiplet fabrics. Maintaining low-loss, low-jitter electrical paths to the photonics requires custom bridge layouts and careful parasitic modeling.
• Mechanical and connector reliability – CPO necessitates fiber attach, alignment tolerance, warpage control, and serviceability. The new detachable fiber coupling and stiffener design point toward deployment models that hyperscalers can maintain at rack scale.
• Overcoming the SerDes ceiling – Electrical SerDes architectures are approaching their practical limit around 112–224 Gbps per lane. Meanwhile, optical I/O scales via wavelength rather than lane rate, giving a more forgiving path to multi-terabit bandwidth.
