The HiWire Consortium is announcing a new effort to standardize CXL Active Electrical Cables and optics.
CXL is expected to enable servers to dramatically expand memory footprints and to share compute, memory and storage resources across rack and row scale installations at line rate.
However, existing passive copper connectivity solutions will not scale to meet this opportunity as they are too short, too bulky and provide insufficient signal integrity for the upcoming PCIe6/CXL3.0 PAM4 64GT/s standard.
The HiWire Consortium CXL Cabling workstream is intended to enable row-scale CXL connectivity with the simplicity and interoperability that HiWire Ethernet AECs are already known for.
“The HiWire Consortium was a key actor in standardizing the Ethernet AECs that much of the cloud runs on today,” said Don Barnetson, Vice President of Product at Credo and organizer of the HiWire Consortium. “Our new CXL workstream will bring this same innovation – enabling plug and play, low-cost, low latency interconnect that allows CXL to span to rack and row scale installations.”
“External connectivity solutions will be key to enhancing the full potential of Intel’s CXL enabled Xeon products,” said Jim Pappas, director of Technology Initiatives at Intel. “Intel is working as a member of the CXL and HiWire Consortium to support these standardization efforts.”
