IBM unveiled a 2 nanometer semiconductor design and process breakthrough based on a new Gate-All-Around (GAA) nanosheet device architecture. The technology is implemented on a 300 millimeter (mm) wafer built at IBM Research’s semiconductor research facility in Albany, New York.
IBM said it is able to fit 50 billion transistors in a space roughly the size of a fingernail. A 2 nm chip node transistor equates to an approximate 45 percent performance improvement over 7 nm chips. This results in an approximate 75 percent power savings, at the same performance level.
IBM Research’s Albany lab features one of the most advanced EUV lithography tools in the industry.
“The IBM innovation reflected in this new 2 nm chip is essential to the entire semiconductor and IT industry,” said Darío Gil, SVP and Director of IBM Research. “It is the product of IBM’s approach of taking on hard tech challenges and a demonstration of how breakthroughs can result from sustained investments and a collaborative R&D ecosystem approach.”
https://www.ibm.com/blogs/research/2021/05/2-nm-chip/?social_post=4791223916&linkId=118030913
