IBM has developed a prototype of the semiconductor industry’s smallest, densest and fastest on-chip dynamic memory device in next-generation, 32-nanometer, silicon-on-insulator (SOI) technology that can offer improved speed, power savings and reliability for products ranging from servers to consumer electronics.
The company said its SOI technology can provide up to a 30 percent chip performance improvement and 40 percent power reduction, compared to standard bulk silicon technology. SOI protects the transistors on the chip with a “blanket” of insulation that reduces electrical leakage, saving power and allowing current to flow through the circuit more efficiently, improving performance.
IBM has fabricated a test chip with an embedded dynamic random access memory (eDRAM) technology that features the industry’s smallest memory cell, and offers density, speed and capacity better than conventional on-chip static random access memory (SRAM) announced in 32nm and 22nm technology, and comparable to what would be expected of an SRAM produced in 15-nanometer technology – three technology generations ahead of chips in volume production today.
IBM said it intends to bring the benefits of its 32-nanometer SOI technology to a wide range of application-specific integrated circuit (ASIC) and foundry clients and will use the technology in chips for its servers.
http://www.ibm.com/technologyhttp://www.soiconsortium.org
