Integrated Device Technology (IDT) announced a new highly-programmable clock generator and jitter attenuator IC offering less than 200 fs of phase noise and designed to provide system design margin for 10 Gbit/s interfaces in wireline and wireless communication networks.
IDT noted that the increased phase noise margin can lower system design constraints and help engineers to minimise bit error rates (BER) while also reducing system costs.
The new IDT 8T49N240 product is the latest member of IDT’s third-generation Universal Frequency Translator (UFT) family. The clock generator and jitter attenuator device is able to produce most common output frequencies from almost any input frequency and targets 10 Gbit/s or multi-lane 40/100 Gbit/s timing applications where 300 fs of phase noise is typically the maximum acceptable level permitted at physical ports. The device is also suitable for 25/28 Gbit/s interfaces.
The 200 fs phase noise specification of the 8T49N240 product therefore provides noise margin to enable engineers to both simplify their clock tree designs and utilise lower cost PCBs.
The 8T49N240 is complemented by IDT’s proven Timing Commander software, a free, intuitive program designed to allow users to configure the device by clicking on blocks, entering desired values and sending the configuration to the device. IDT also offers a web-based tool that allows customers to quickly generate custom part numbers to match their specific configurations.
The 8T49N240 product features a 6 x 6 mm package footprint that requires less PCB area than other comparable solutions. The 8T49N240 and evaluations boards are available immediately.
