Infineon Adds Resilient Packet Ring Chips

Infineon Technologies introduced a family of PoS Framer/RPR MAC chips that are compliant with Draft 2.1 of the proposed IEEE 802.17 Resilient Packet Ring (RPR) standard. Infineon’s Frea chips perform the PoS (Packet-over-SONET) framer, RPR MAC (Media Access Control) and XAUI SerDes (serializer/deserializer) functions that are necessary to deploy RPR in metro networks and WANs. The chips eliminate the need for external memory by including 1 Megabyte of memory on-chip for RPR operation and also a 16-bit 800 MHz SPI-4.2 system interface and a 4-bit 3.125 GHz mate (XAUI) interface, eliminating the need for an external SerDes to link the two chips required for a full RPR implementation. Infineon said its solution supports both the IEEE 802.17 RPR standard (Draft 2.1) and the RFC 2892 Spatial Reuse Protocol (SRP) protocol. It can also operate in a PoS framer-only mode.
http://www.infineon.com/frea