Intel announced the first implementation of its PowerVia backside power delivery technology in a product-like test chip.
PowerVia solves the growing issue of interconnect bottlenecks in area scaling by moving power routing to the backside of a wafer.
Intel said PowerVia was tested on its own internal test node to debug and ensure good functionality of the technology before its integration with RibbonFET in Intel 20A. After fabrication and testing on a silicon test chip, PowerVia was confirmed to bring a remarkably efficient use of chip resources with greater than 90% cell utilization and major transistor scaling, enabling chip designers to achieve performance and efficiency gains in their products.
Intel plans to introduce PowerVia on the Intel 20A process node in the first half of 2024.
“PowerVia is a major milestone in our aggressive ‘five nodes in four years’ strategy and on our path to achieving a trillion transistors in a package in 2030. Using a trial process node and subsequent test chip enabled us to de-risk backside power for our leading process nodes, placing Intel a node ahead of competitors in bringing backside power delivery to market,” states Ben Sell, Intel vice president of Technology Development.
