Intel detailed progress on its “Moorestown” platform, scheduled for 2010 and targeting MIDs and smartphones. The chip will leverage Distributed Power Gating technology that along with other techniques will help to achieve up to a 50x improvement in platform idle power reduction compared to Intel’s first generation “Menlow” platform. Intel said these reductions are enabling it to establish new thresholds in ultra low power while making it possible to run the full Internet and media-rich applications in handheld devices.
Intel’s third generation ultra-low power platform, codenamed “Medfield,” will be a single-chip 32nm system-on-chip (SoC) design expected in 2011 that will enable a much smaller form factor and lower power designs than Moorestown, helping extend Intel squarely into smartphone segments.
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