Intel introduced its new Intel an”Agilex” field programmable gate array (FPGA) family targetted at embedded, network and data center markets.
The Intel Agilex family combines FPGA fabric built on Intel’s 10nm process with innovative heterogeneous 3D SiP technology. This provides the capability to integrate analog, memory, custom computing, custom I/O, and Intel eASIC device tiles into a single package with the FPGA fabric.
Intel delivers a custom logic continuum with reusable IPs through a migration path from FPGA to structured ASIC. One API provides a software-friendly heterogeneous programming environment, enabling software developers to easily access the benefits of FPGA for acceleration.
Intel said the new product is the first FPGA to support Compute Express Link, a cache and memory coherent interconnect to future Intel Xeon Scalable processors.
Agilex also supports 2nd-generation HyperFlex Architecture, which offers up to 40 percent higher performance, or up to 40 percent lower total power compared with Intel Stratix 10 FPGAs. The new Agilex family is also the only FPGA supporting hardened BFLOAT16 and up to 40 teraflops of digital signal processor (DSP) performance (FP16). It also supports Peripheral component interconnect express (PCIe) Gen 5.
The Agilex transceiver supports up to 112 Gbps data rates. Advanced memory support includes DDR5, HBM, and Intel Optane DC persistent memory.
“The race to solve data-centric problems requires agile and flexible solutions that can move, store and process data efficiently. Intel Agilex FPGAs deliver customized connectivity and acceleration while delivering much needed improvements in performance and power1,2 for diverse workloads,” stated Dan McNamara, Intel senior vice president, Programmable Solutions Group.
