Marvell’s first 3nm silicon is now in fabrication with Taiwan Semiconductor Manufacturing Company (TSMC) on its 3nm shuttle. Marvell said this advancement will enable it to develop some of the most advanced multi-die, multi-chiplet systems-in-package (SiP) for its infrastructure products and co-development of custom ASIC solutions optimized for some of the most challenging infrastructure use cases, such as machine learning.
The 3nm platform includes foundational IP building blocks such as long reach SerDes, PCIe Gen6 PHY, and several standards-based die-to-die interconnect technologies for managing data flow across the data infrastructure.
This 3nm development follows numerous 5nm solutions from Marvell – in production or development – that span electro-optics, switch, PHY, compute, 5G baseband, and storage products, as well as a wide range of custom ASIC programs.
Additionally, this IP portfolio is compatible with 2.5D packaging technologies such as TSMC’s leading-edge 2.5D Chip-on-Wafer-on-Substrate (CoWoS)
Hugh Durdan provides a perspective.
